1. Field of the Invention
The present invention relates to a structure of a basic cell of a gate array type semiconductor device (gate array semiconductor device) and an art characterized by a layout method thereof.
2. Description of the Related Art
With the improving technology for microminiaturizing an LSI (Large Scale Integration) circuits, the number of gates mounted per unit area, namely, “integration”, is increasing as indicated by Moore's Law. However, as the microminiaturization reaches a submicron scale and further a nano-order scale, the layout of a basic cell inevitably finds some places that do not match a gate scaling because of an available wiring method and the electrical characteristics of a semiconductor circuit. Hence, there has been a problem in that higher integration that successfully matches a higher level of microminiaturization cannot be achieved unless sophisticated design of the structure of a basic cell for the layout is accomplished.
As a solution to the above problem, there is, for example, a technique disclosed in Japanese Unexamined Patent Publication No. 10-335612. According to the technique, a well drawing region is disposed at an outer corner of each gate cell and a power bus is also disposed on the outer side of the gate cell so as to allow the well drawing region and the power bus to be shared. This arrangement makes it possible to reduce the number of transistors in a single cell, which is repeated, from 8 to 4.
According to another technique disclosed in, for example, Japanese Unexamined Patent Publication No. 8-23082, a wiring route is simplified by omitting the wiring connected to the source/drain region of a transistor from a power source wire in a gate layout so as to attain a higher level of integration by restraining an increase in the wiring area. In this case, the source/drain region is laid out such that it projects at a gate-shaped top portion, thus obviating the need for the wiring from the power source wire. Thus, no wiring layers interfere with the wiring route of a logic circuit, so that the freedom of wiring is improved and the congestion problem of wires can be solved, resulting in higher integration.
These techniques, however, are intended for improving integration by devising an inventive layout structure so as to reduce the area required for wiring, and the sizes of the elements (basic cells) making up a gate array remain unchanged.